Synchronous DRAMs require a column access pulse which is internally timed in order to connect the DRAM sense amplifiers to a databus of the DRAM. Typically a simple pulse generator with an internal delay which defines the pulse width has been used for this purpose.
To operate a DRAM at very fast speeds, such as at 100 MHz, pulses generated by the pulse generator must be extremely short. Some DRAM chips are manufactured which do not meet the required speed specification, but can operate satisfactorily at slower speeds, such as at 80 MHz. In the past, such chips would be rejected since they could not operate from the very short pulses resulting from the clock generator, thus reducing yield.